Digital Verification Engineer (CKD/RCD)
Responder al anuncioOur client is seeking a Digital Verification Engineer to define and lead the development of the digital verification framework and infrastructure for complex digital and mixed-signal ICs. This role involves using cutting-edge technologies with industry-standard ASIC tools to design and verify products that may include power management, signal management, and mixed-signal functions.
MPS products encompass a wide array of applications, such as switching regulators, sensors, motor control, display drivers, audio amplifiers, and power management ICs for rapidly growing portable and non-portable markets like notebooks, cell phones, telecom, digital cameras, automobiles, and network equipment.
Essential Functions
- Define and develop UVM and System Verilog-based digital verification environments.
- Standardize, define, develop, and document verification IPs (VIPs).
- Integrate VIPs into the project's digital verification environment.
- Define digital verification metrics for RTL and gate-level verification.
- Develop and define test plans.
- Automate digital verification and create supporting scripts.
- Define, develop, and manage regression infrastructure.
- Collaborate closely with senior digital and analog designers to develop VIP models.
- Lead the digital verification team and supervise verification tasks across multiple projects.
- Review digital verification metrics and results for multiple projects.
- Define and design top-level digital verification tests.
- Analyze and debug test results, code coverage, and functional coverage.
- Estimate, plan, and schedule digital verification tasks to meet tape-out dates.
Qualifications
- PhD, BS, or MS in Electrical Engineering with a focus on Digital Design/VLSI coursework.
- 3+ years of strong experience in both RTL and gate-level verification.
- Proficient in digital verification industry languages (UVM, System Verilog) and standards.
- Expertise in digital verification skills and areas: constraint random tests, SV assertions, coverage metrics, analog and digital DV modeling, DV test plans, regression analysis and reports, UVM DV agents (monitor, driver, scoreboard), etc.
- Comprehensive knowledge and experience across the entire digital design flow: specification definition, RTL verification, synthesis, P&R, gate-level verification, power estimation, ATPG generation and simulation, AMS simulations, etc.
- Excellent knowledge and use of industry-standard ASIC tools/flow: digital simulators, synthesis tools, DFT, LEC, STA, etc.
- Strong scripting and automation skills using TCL, Python, or C/C++.
- Leadership skills to technically guide the digital verification team and mentor junior designers.
- Strong written and verbal communication skills, with an emphasis on teamwork and collaboration.
Preferred Experience
- Embedded design and/or firmware development.
- Knowledge of power management industry/applications.
- Familiarity with I2C, I3C, SPI, USB, PMBUS.
- Experience with GitLab.
This role can be based at either of the following office locations:
- Barcelona, Spain
- Porto/Lisbon, Portugal
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