FPGA engineer (Junior/Senior)- RiscV IP, Barcelona
FPGA engineer (Junior/Senior)- RiscV IP en Barcelona.
Perfil buscado (Hombre/Mujer) Integrate RTL code releases into new FPGA designs Configure FPGA peripherals for maximizing the performance of the RISC-V prototyping solutions Implement new RTL modules to provide the RISC-V core under emulation/prototyping with the optimal I/O configurations Interact with other teams to understand their requirements for new features and on how that can be leveraged into the FPGA designs Maintain and further improve our in-house FPGA resource pool Provide support and develop new features to be used in demonstration systems for company clients International company based in Barcelona specialized in Risc-V Great oportunity to join a top engineers team +3 years of industrial experience Bachelors Matser or PhD degree in computer science Experience working with Xilinx (or Altera) FPGAs using Xilinx Vivado (or Altera Quartus). Experience in using FPGA Integrated Logic Analyser probes Knowledge of AXI4/AXI4-Lite UART I2C SPI protocols Proficient with HDL languages such as Verilog/SystemVerilog (or VHDL) Experienced with FPGA timing and placement constraints using SDC syntax Experienced in TCL and Bash scripting for FPGA Experienced with version control Experienced with Linux based operating systems / distributions Knowledge of C/C++ and Python
International company based in BCN with almost 10 years experience within semiconductor industry. Our client is european supplier of RISC-V IP cores Career plan. Competitive salary according to your experience VS salary expectations Bonus based on performance. Social benefits
Xilinx, Altera,
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